HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.1.1.10. VSI_CONTROL (0x0D)

Table 74.  VSI_CONTROL (0x0D)
Name Bit(s) Access Description Reset
reserved 31:1 - - -
VSI disable 0 RW When set to 1, HDMI TX core does not send VSI infoframes from the VSI_PACKET registers.

When set to 0, HDMI TX core sends VSI infoframes from the VSI_PACKET registers

0x0

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