HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.3.1.27. SCDC_FRL_STATUS (0x2E)

Table 147.  SCDC_FRL_STATUS (0x2E)
Name Bit Access Description Reset
Reserved 31:12 - - -
SCDC FRL FFE level 11:8 RO

Indicates the maximum TxFFE level supported by the source at current FRL rate.

These bits correspond to the SCDC sink configuration register 0x31 bits 4-7

0x0
SCDC FRL rate 7:4 RO

Indicates the FRL rate (link rate and number of lanes)that the RX core is running.

0: Disable FRL

1: Fixed rate link at 3 Gbps per lane on 3 lanes

2: Fixed rate link at 6 Gbps per lane on 3 lanes

3: Fixed rate link at 6 Gbps per lane on 4 lanes

4: Fixed rate link at 8 Gbps per lane on 4 lanes

5: Fixed rate link at 10 Gbps per lane on 4 lanes

6: Fixed rate link at 12 Gbps

0x0
SCDC FRL locked 3:0 RO

Each bit indicates the corresponding FRL lane achieving lock.

For 3-lane mode, the RX core asserts the lock bit when it detects SR or SSB followed by 680 FRL Character Periods, repeating for 3 times. Bit 3 is never asserted at 3-lane mode.

For 4-lane mode, the RX core asserts the lock bit when it detects SR or SSB followed by 510 Character Periods.

0x0

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