HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

6.2. Sink Interfaces

The table lists the port interfaces of the sink.
Table 60.  Sink Interfaces N is the number of pixels per clock.

Interface

Port Type

Clock Domain

Port

Direction

Description

Reset Reset reset Input Main asynchronous reset input.
Note: Asserting the reset input resets the SCDC register.
Reset reset_vid   Reset input for the video domain.
Note: This signal is only available when Support FRL = 0.
Clock Clock ls_clk Input Link speed clock input.

This port is only used when Support FRL = 0.

The out_c(3), out_r(2), out_g(1), and out_b(0)TMDS/FRL encoded data inputs run at this clock frequency.

ls_clk frequency = data rate per lane/20

This signal connects to the transceiver output clock only if TMDS Bit Rate is above the minimum transceiver data rate, which means no oversampling is required.

This signal should connect to a PLL output clock that meets the vid_clk relationship if TMDS Bit Rate is below the minimum transceiver data rate, which means oversampling is required.

In TMDS mode, data rate per lane is a function of pixel frequency and color depth ratio.

Data rate per lane = Pixel frequency * 10 * Color depth ratio.

  • 8 bpc: Color depth ratio = 1
  • 10 bpc: Color depth ratio = 1.25
  • 12 bpc: Color depth ratio = 1.5
  • 16 bpc: Color depth ratio = 2
Note: The ls_clk signal is 3 bits wide for Intel® Quartus® Prime Pro Edition software versions 19.2 and earlier.

Refer to Table 40 for more details.

Clock vid_clk Input Video data clock input.

When Support FRL = 0, vid_clk frequency = data rate per lane/transceiver width/color depth ratio.

  • For RGB and YCbCr 4:4:4/4:2:2 transport: vid_clk frequency = (data rate per lane/transceiver width)/color depth ratio.
  • For YCbCr 4:2:0 transport: vid_clk frequency = ((data rate per lane/transceiver width)/color depth ratio)/2.
  • vid_clk needs to be synchronous to ls_clk.

When Support FRL = 1,vid_clk frequency = 225 MHz.

  • vid_clk runs at the maximum frequency across all resolutions and FRL rates.
  • The video data is qualified by the vid_valid signal.
  • vid_clk can be asynchronous to ls_clk and frl_clk.
Clock frl_clk Input

Clock supplied to the FRL path.

FRL clock frequency = (data rate * number of lane)s / (FRL characters per clock * 18).

frl_clk needs to be synchronous to clk_b.

Note: The number of lanes is always 4. For FRL rates 3, 4, 5, and 6, all 4 FRL lanes are used to transmit data. For FRL rates 1 and 2, only 3 FRL lanes are used to transmit data, and the 4th lane is unused.
Clock clk_b Input

Transceiver recovered clock from the "Blue" data channel.

Clock clk_g Input

Transceiver recovered clock from the "Green" data channel.

Clock clk_r Input

Transceiver recovered clock from the "Red" data channel.

Clock clk_c Input

Transceiver recovered clock from the clock data channel.

Clock i2c_clk Input Avalon-MM SCDC Management Interface clock input.
Video Data Port Conduit vid_clk vid_data[N*48-1:0] Output

Video 48-bit pixel data output port. For N pixels per clock, this port produces N 48-bit pixels per clock.

Conduit vid_clk vid_de[N-1:0] Output Video data enable output that indicates active picture region.
Conduit vid_clk vid_hsync[N-1:0] Output Video horizontal sync output.
Conduit vid_clk vid_vsync[N-1:0] Output Video vertical sync output.
Conduit vid_clk vid_valid Output

Indicates if the video data is valid. When in TMDS mode and vid_clk is running at the actual pixel clock, this signal should always be asserted.

When you generate the video data at a frequency higher than the actual pixel clock, use vid_valid to qualify the validity of the video data. vid_valid and vid_clk guarantee the exact pixel clock rate.

Conduit vid_clk locked Output

Indicates that the HDMI sink core is locked to the TMDS or FRL signals with successful lane deskew and word alignment.

Note: The locked[2:0] signal is 3 bits wide for Intel® Quartus® Prime Pro Edition software versions 19.2 and earlier, where each bit represents the locked status of a TMDS color channel.
Conduit vid_clk vid_lock Output Asserted when the length or duration of vid_de is consistent for 3 frames. If the length or duration of vid_de is inconsistent for 2 frames, this signal deasserts.
TMDS/FRL Data Port 6 Conduit

Support FRL =1: clk_b

Support FRL =0: ls_clk[0]

in_b[transceiver width-1:0] Input TMDS encoded blue channel (0) input or FRL encoded channel 0.

When in TMDS mode, this signal is TMDS encoded blue channel (0) output.

When in FRL mode, this signal is FRL lane 0.

  • When Support FRL = 0, transceiver width is configured to 20 bits.
  • When Support FRL = 1, transceiver width is configured to 40 bits.
Note: For TMDS mode, only the 20 bits from the least significant bits are used. For FRL mode, all 40 bits are used.
Conduit

Support FRL =1: clk_b

Support FRL =0: ls_clk[0]

in_g[transceiver width-1:0] Input TMDS encoded green channel (1) input or FRL encoded channel 1.

When in TMDS mode, this signal is TMDS encoded green channel (1) output.

When in FRL mode, this signal is FRL lane 1.

  • When Support FRL = 0, transceiver width is configured to 20 bits.
  • When Support FRL = 1, transceiver width is configured to 40 bits.
Note: For TMDS mode, only the 20 bits from the least significant bits are used. For FRL mode, all 40 bits are used.
Conduit

Support FRL =1: clk_b

Support FRL =0: ls_clk[0]

in_r[transceiver width-1:0] Input TMDS encoded red channel (2) input or FRL encoded channel 2.

When in TMDS mode, this signal is TMDS encoded red channel (2) output.

When in FRL mode, this signal is FRL lane 2.

  • When Support FRL = 0, transceiver width is configured to 20 bits.
  • When Support FRL = 1, transceiver width is configured to 40 bits.
Note: For TMDS mode, only the 20 bits from the least significant bits are used. For FRL mode, all 40 bits are used.
Conduit clk_c in_c[transceiver width-1:0] Input

When in TMDS mode, this signal is unused.

When in FRL mode, this signal is FRL lane 3.

When Support FRL = 1, transceiver width is configured to 40 bits

Conduit

Support FRL =1: clk_b

Support FRL =0: ls_clk[0]

in_lock Input

Indicates the HDMI RX core is ready to operate. This signal should be driven by the ready signal from the transceiver reset controller that indicates transceiver are locked.

Note: The in_lock signal is 3 bits wide for Intel® Quartus® Prime Pro Edition software versions 19.2 and earlier.
Decoder Status Port Conduit

Support FRL =1: clk_b

Support FRL =0: ls_clk[0]

ctrl[N*6-1:0] Output DVI (mode = 0) status signals that overwrite the control and synchronization character in the green and red channels.
Bit-Field n=0,1.....N-1

n*6+5

CTL3

n*6+4

CTL2

n*6+3

CTL1

n*6+2

CTL0

n*6+1

Reserved (0)

n*6

Reserved (0)

Refer to the HDMI 1.4b Specification for more information.

Conduit

Support FRL =1: clk_b

Support FRL =0: ls_clk[0]

mode Output

Indicates the encoding mode of the incoming TMDS signals.

  • 0: DVI
  • 1: HDMI

This signal is always 1 in FRL mode.

Link Training Control and Status Port Conduit i2c_clk scdc_frl_ffe_levels[3:0] Input Indicates the maximum TxFFE level supported by the source at current FRL rate, These bits correspond to the SCDC sink configuration register 0x31 bits 4-7.
Conduit i2c_clk scdc_frl_rate[3:0] Output

Indicates the FRL rate (link rate and number of lanes) that the RX core is running.

  • 0: Disable FRL
  • 1: Fixed rate link at 3 Gbps per lane on 3 lanes
  • 2: Fixed rate link at 6 Gbps per lane on 3 lanes
  • 3: Fixed rate link at 6 Gbps per lane on 4 lanes
  • 4: Fixed rate link at 8 Gbps per lane on 4 lanes
  • 5: Fixed rate link at 10 Gbps per lane on 4 lanes
  • 6: Fixed rate link at 12 Gbps per lane on 4 lanes
Conduit i2c_clk scdc_frl_locked[3:0] Output

Each bit indicates the corresponding FRL lane achieving lock.

  • For 3-lane mode, the RX core asserts the lock bit when it detects SR or SSB followed by 680 FRL Character Periods, repeating for 3 times. Bit 3 is never asserted at 3-lane mode.
  • For 4-lane mode, the RX core asserts the lock bit when it detects SR or SSB followed by 510 Character Periods, repeating for 3 times.
Conduit i2c_clk scdc_frl_ltp_req[15:0] Input

Write to the SCDC status flags 0x41 and 0x42 to request the source to transmit specific link training pattern. Set scdc_frl_ltp_req[15:0] 0x0000 to pass the link training process.

  • Bit [15:12]: Link training pattern for lane 3 (SCDC status flag 0x42 bit[7:4])
  • Bit [11:8]: Link training pattern for lane 2 (SCDC status flag 0x42 bit[3:0])
  • Bit [7:4]: Link training pattern for lane 1 (SCDC status flag 0x41 bit[7:4])
  • Bit [3:0]: Link training pattern for lane 0 (SCDC status flag 0x41 bit[3:0])
  • By default this port is disabled. Sink will always request link training pattern 0x5678. To enable other link training pattern please contact Sale.
  • Sink does not support FFE. Pattern 0xEEEE are not supported.
  • Sink link training process will not automatically change to other FRL rate. Pattern 0xFFFF are not supported.
Conduit i2c_clk scdc_frl_flt_ready Input

Set this bit to 1 when the HDMI RX core is ready for the link training process. When asserted, the FLT_Ready bit in the SCDC status flag 0x40 bit 6 is set to 1, the FRL start flag is cleared, and the FLT update flag is set for the link training process.

Conduit i2c_clk scdc_frl_src_test_config[7:0] Input

Configure the Source Test Configuration register (SCDC register 0x35)

  • Bit 7 : FRL_Max
  • Bit 6: SDC_FRL_Max
  • Bit 5: FLT_no_timeout
  • Bit 4: Reserved
  • Bit 3: TxFFE_No_FFE
  • Bit 2: TxFFE_De_Emphasis_only
  • Bit 1: TxFFE_Pre_Shoot_Only
  • Bit 0: Reserved
For more information about these bits, refer to the 10.4.1.6.1 Source Test Configuration Request section of the HDMI 2.1 Specifications.

SCDC Control Port

Conduit i2c_clk in_5v_power Input Detects the presence of 5V input voltage.
Conduit i2c_clk rx_hpd_req Output Indicates the Hot Plug Detect (HPD) status. This signal should be driven to the HPD pin on the HDMI connector.
  • Sink will deassert rx_hpd_req if in_5v_power is low or after reset.
  • Sink will assert rx_hpd_req after 1 second in_5v_power is detected, or after reset
  • Contact sale team if want to change the HPD duration.
Conduit i2c_clk TMDS_Bit_clock_Ratio Output

Indicates if the TMDS Bit Rate is greater than 3.4 Gbps

  • 0: (TMDS Bit Rate) / (TMDS Clock Rate) ratio is 10 or FRL mode
  • 1: (TMDS Bit Rate) / (TMDS Clock Rate) ratio is 40

Avalon-MM SCDC Management Interface 7

Avalon-MM i2c_clk scdc_i2c_addr[7:0] Input

Address.

Avalon-MM i2c_clk scdc_i2c_r Input Assert to indicate a read transfer.
Avalon-MM i2c_clk scdc_i2c_rdata[7:0] Output Data driven from the core in response to a read transfer.
Avalon-MM i2c_clk scdc_i2c_w Input Assert to indicate a write transfer.
Avalon-MM i2c_clk scdc_i2c_wdata[7:0] Input Data for write transfers.
Auxiliary Data Port (Applicable only when you enable Support auxiliary parameter) Conduit aux_clk aux_valid Output Auxiliary data channel valid output to qualify the data.
Conduit aux_clk aux_data[71:0] Output Auxiliary data channel data output.

For information about the bit-fields, refer to Figure 52.

Conduit aux_clk aux_sop Output Auxiliary data channel start-of-packet output to mark the beginning of a packet.
Conduit aux_clk aux_eop Output Auxiliary data channel end-of-packet output to mark the end of a packet.
Conduit aux_clk aux_error Output Asserted when there is auxiliary data channel CRC error.
Auxiliary Status Port (Applicable only when you enable Support auxiliary parameter) 8 Conduit aux_clk gcp[5:0] Output General Control Packet output.

For information about the bit-fields, refer to Table 23.

Conduit aux_clk

info_avi[122:0] (Support FRL = 1)

info_avi[111:0] (Support FRL = 0)

Output Auxiliary Video Information InfoFrame output.

For information about the bit-fields, refer to Table 24.

Conduit aux_clk info_vsi[60:0] Output Vendor Specific Information InfoFrame output.
For information about the bit-fields, refer to Table 26.
Auxiliary Memory Interface (Applicable only when you enable Support auxiliary parameter) 8 Conduit aux_clk aux_pkt_addr[6:0] Output Auxiliary packet memory buffer address output.
Conduit aux_clk aux_pkt_data[71:0] Output Auxiliary packet memory buffer data output.
Conduit aux_clk aux_pkt_wr Output Auxiliary packet memory buffer write strobe output.
Audio Port (Applicable only when you enable Support auxiliary and Support audio parameters)8 Conduit aux_clk audio_CTS[19:0] Output Audio CTS value output.
Conduit aux_clk audio_N[19:0] Output Audio N value output.
Conduit aux_clk audio_data[255:0] Output Audio data output.

For audio channel values, refer to Table 39.

Conduit aux_clk audio_de Output Audio data valid output.
Conduit aux_clk audio_metadata[164:0] Output Additional information related to 3D audio and MST audio.

For information about the bit-fields, refer to Table 29, Table 30, and Table 31.

Conduit aux_clk audio_format[4:0] Output Indicates 3D audio status and the audio format detected.
Bit-Field Description
4 The core asserts to indicate the first 8 channels of each 3D audio sample.
3:0

For information about the bit-fields, refer to Table 27.

 
Conduit aux_clk audio_info_ai[47:0] Output Audio InfoFrame output bundle.

For information about the bit-fields, refer to Table 28.

PHY Control Interface Port Conduit

Support FRL:clk_b

Support FRL =0:ls_clk

os Input

Indicates to the core that the current receiving data rate requires downsampling with a factor of 5.

Assert this signal when the receiving TMDS Bit Rates is less than 1 Gbps.

I2C Slave Interface Port Conduit i2c_scl Input

SCL signal from I2C bus on the HDMI connector.

This signal is not available if you turn off the Include I2C parameter.

Conduit i2c_sda Inout

SDA signal from I2C bus on the HDMI connector.

This signal is not available if you turn off the Include I2C parameter.

  i2c_clk edid_i2cslv_rdata[7:0] Input

Connect this signal to the output q port of an EDID RAM. This signal returns the value from a certain address in the RAM to the internal I2C slave.

This signal is available only if you turn on the Include I2C parameter and turn off the Include EDID RAM parameter.

Conduit i2c_clk edid_i2cslv_addr[31:0] Output

Connect this signal to the output address port of an EDID RAM. This signal indicates the address that the I2C slave would access to the RAM.

This signal is available only if you turn on the Include I2C slave parameter and turn off the Include EDID RAM parameter.

Conduit i2c_clk tmds_config_trans_det Output

Indicates that there is a new write operation to the SCDC address offset 0x20 (TMDS configuration).

Connect this signal to a reconfiguration controller to restart the reconfiguration flow.

This signal is not available if you turn off the Include I2C parameter.

EDID RAM Interface Port Conduit i2c_clk edid_ram_access Input

Assert this signal when you are reading or writing to the EDID RAM. Deassert this signal when the read and write operations are complete.

Asserting this signal would trigger an HPD event to the source. When you deassert this signal, the source reads the new EDID which you have just written into the RAM.

This signal is not available if you turn off the Include EDID RAM parameter.

Avalon® -MM i2c_clk edid_ram_address Input

Avalon® memory mapped interface to the EDID RAM. Connect these signals to an Avalon® memory mapped master, such as NIOS, to perform read and write operation to the EDID RAM.

These signals are not available if you turn off the Include EDID RAM parameter.

Avalon® -MM i2c_clk edid_ram_read Input
Avalon® -MM i2c_clk edid_ram_write Input
Avalon® -MM i2c_clk edid_ram_waitrequest Output
Avalon® -MM i2c_clk edid_ram_readdata[7:0] Output
Avalon® -MM i2c_clk edid_ram_writedata[7:0] Input
AXI4-Stream Video (Only applicable when Enable Active Video Protocol = AXIS-VVP Full) AXI4 Stream axi4s_clk axi4s_vid_out_tvalid Output AXI4-Stream video interface. The transfer protocol follows AXI4-Stream (full variant) as indicated in Intel FPGA Streaming Video Protocol Specification. Refer to the link in Related Information.
AXI4 Stream axi4s_clk axi4s_vid_out_tready Input
AXI4 Stream axi4s_clk axi4s_vid_out_tlast Output
AXI4 Stream axi4s_clk axi4s_vid_out_tuser Output
AXI4 Stream axi4s_clk axi4s_vid_out_tdata Output
AXI4-Stream Auxiliary (Only applicable when Enable Active Video Protocol = AXIS-VVP Full) AXI4 Stream mgmt_clk axi4s_aux_out_tvalid Output AXI4-Stream auxiliary interface. Refer to section RX AXI4-Stream Auxiliary Bridge for the AXI4 streaming auxiliary transfer protocol.
AXI4 Stream mgmt_clk axi4s_ aux _out_tready Input
AXI4 Stream mgmt_clk axi4s_ aux _out_tlast Output
AXI4 Stream mgmt_clk axi4s_ aux _out_tuser Output
AXI4 Stream mgmt_clk axi4s_ aux _out_tdata Output

Avalon Memory-Mapped Control

(Only applicable when Enable Active Video Protocol = AXIS-VVP Full)
Avalon® - MM mgmt_clk av_mm_control_write Input Avalon memory-mapped interface to access to HDMI RX core Avalon memory-mapped demultiplexer, which provide read or write access to EDID RAM, HDMI sink registers, clocked video to AXI4-stream converter, HDCP (reserved for future use). The addressing mode for this Avalon Memory-Mapped interface is double-word addressing.
Avalon® - MM mgmt_clk av_mm_control_read Input
Avalon® - MM mgmt_clk av_mm_control_address Input
Avalon® - MM mgmt_clk av_mm_control_writedata Input
Avalon® - MM mgmt_clk av_mm_control_readdata Output
Avalon® - MM mgmt_clk av_mm_control_waitrequest Output
Avalon® - MM mgmt_clk av_mm_control_debugaccess Input
Avalon® - MM mgmt_clk av_mm_control_lock Input
Avalon® - MM mgmt_clk av_mm_control_byteenable Output
HDCP Port (Applicable only when you enable Support HDCP 2.3 or Support HDCP 1.4 parameters) Reset hdcp_reset Input Main asynchronous reset.
Clock hdcp_i2c_clk Input

HDCP clock for control and status registers.

Typically, shares the I2C slave clock (100 MHz).

crypto_clk Input

HDCP 2.3 clock for authentication and cryptographic layer.

You can use any clock with a frequency up to 200 MHz.

Not applicable for HDCP 1.4.

Note: The clock frequency determines the authentication latency.
rpt_msg_clk Input

HDCP clock for the Repeater registers in the Control and Status Register layer.

Typically, shares the clock (100 MHz) that drives the repeater downstream Nios II processor.

Available only when you turn on the SUPPORT_REPEATER parameter.

Avalon-MM hdcp_i2c_clk hdcp_i2c_addr[7:0] Input

The Avalon-MM slave port that provides access to HDCP registers.

The I2C slave must drive this port for HDMI application.

hdcp_i2c_wr Input
hdcp_i2c_rd Input
hdcp_i2c_wrdata[7:0] Input
hdcp_i2c_rddata[7:0] Output
Conduit hdcp_i2c_clk i2c_stop_det Input Assert this signal to indicate the stop condition for each I2C command.
Avalon-MM rpt_msg_clk rpt_msg_addr[7:0] Input

The Avalon-MM slave port that provides access to the Repeater registers, mainly for Receiver ID List and RxInfo. This interface is expected to operate at repeater downstream Nios II processor clock domain.

Because of the extremely large bit portion of message, the IP transfers the message in burst mode with full handshaking mechanism. Write transfers always have a wait time of 0 cycle while read transfers have a wait time of 1 cycle.

The addressing should be accessed as word addressing in the Platform Designer flow. For example, addressing of 4 in the Nios II software selects the address of 1 in the slave.

rpt_msg_wr Input
rpt_msg_rd Input
rpt_msg_wrdata[31:0] Input
rpt_msg_rddata[31:0] Output
Conduit (Key) crypto_clk kmem_wait Input

Always keep this signal asserted until the key is ready to be read.

This signal is not available if you turn on the Support HDCP Key Management parameter.

kmem_rdaddr[7:0] (HDCP 2.3)

kmem_rdaddr[13:8] (HDCP 1.4)

Output Key read address bus.

This signal is not available if you turn on the Support HDCP Key Management parameter.

kmem_q[31:0] (HDCP 2.3)

kmem_q[87:32] (HDCP 1.4)

Input

32-bit (HDCP 2.3) or 56-bit (HDCP 1.4) data for read transfers.

Read transfer always have a wait time of 1 cycle.

This signal is not available if you turn on the Support HDCP Key Management parameter.

Avalon-MM hdcp_i2c_clk hdcp1_kmem_wr Input

The Avalon-MM slave port provides write access to internal HDCP 1.4 key storage. Write transfers always have a wait time of 0.

The Avalon® memory-mapped master access the addressing as word addressing in the Platform Designer flow.

For example, addressing of 4 in the Avalon® memory-mapped master selects the address of 1 in the slave.

These signals are only available if you turn on the Support HDCP Key Management parameter and the Support HDCP 1.4 parameter

hdcp1_kmem_wrdata[31:0] Input
hdcp1_kmem_addr[6:0] Input
Avalon-MM hdcp_i2c_clk hdcp2_kmem_wr Input

The Avalon® memory-mapped slave port that provides write access to internal HDCP 2.3 key storage. Write transfers always have a wait time of 0.

The Avalon® memory-mapped master access the addressing as word addressing in the Platform Designer flow.

For example, addressing of 4 in the Avalon® memory-mapped master selects the address of 1 in the slave.

These signals are only available if you turn on the Support HDCP Key Management parameter and the Support HDCP 2.3 parameter.

hdcp2_kmem_wrdata[31:0]

Avalon®

Input
hdcp2_kmem_addr[7:0] Input
Conduit ls_clk hdcp1_enabled Output This signal is asserted by the IP if the incoming video and auxiliary data are HDCP 1.4 encrypted.
hdcp2_enabled Output This signal is asserted by the IP if the incoming video and auxiliary data are HDCP 2.3 encrypted.
streamid_type Output
  • 0: The received stream type is 0.
  • 1: The received stream type is 1.
hdcp_i2c_clk hdcp1_disable Input Assert this signal to disable the HDCP 1.4 IP.
Note: You must reset the HDCP IP (hdcp_reset) and trigger a Hot Plug event after toggling this signal.
hdcp2_disable Input Assert this signal to disable the HDCP 2.3 IP.
Note: You must reset the HDCP IP (hdcp_reset) and trigger a Hot Plug event after toggling this signal.
6 Connect to the transceiver data output if no oversampling is required. If oversampling is required, the port should connect to a DCFIFO and an oversampling user logic before connecting to a transceiver data output. Refer to Sink Clock Tree for more information.
7 Refer to HDMI 2.0b Specification Section 10.4 for address and data bit mapping.
8

aux_clk = ls_clk (Support FRL = 0)

aux_clk = vid_clk (Support FRL = 1)

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