HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

6.1.25. RX Auxiliary User Packetizer

The user defined packet interface provides a means for the host processor to extract predefined HDMI data packet types into a buffer to be read from the memory-mapped Avalon interface.

This block includes RX auxiliary packet filter block to filter the packet type to be captured to user packet buffer. The type of packets to be captured is defined by the packet filter register. Refer to USER_PACKET_FILTER for more information

When a packet with the same type as that defined by the packet filter register, it is stored in the buffer. When this happens, user packet buffer level registeris incremented, and it also triggers interrupt. Packet buffer fullregister and packet buffer empty registercorrespondto the buffer full and empty signals respectively.

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