HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

5.1.16.2. Clock Enable Generator

The clock enable generator is a logic block that generates a clock enable pulse.

This clock enable pulse asserts every number of clock cycles defined by the oversampling factor and serves as a read request signal to clock the data out from the DCFIFO.

Figure 29. Oversampling Blocks and Clock Enable Blocks When Support FRL = 0
Figure 30. Oversampling Blocks and Clock Enable Block When Support FRL = 1

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