HDMI Intel® FPGA IP User Guide

ID 683798
Date 3/03/2023
Public

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5.1.16.2. Clock Enable Generator

The clock enable generator is a logic block that generates a clock enable pulse.

This clock enable pulse asserts every number of clock cycles defined by the oversampling factor and serves as a read request signal to clock the data out from the DCFIFO.

Figure 29. Oversampling Blocks and Clock Enable Blocks — FRL Support Turned Off
Figure 30. Oversampling Blocks and Clock Enable Block — FRL Support Turned On
Table 36.  Oversampling Block Signals Description
Signal Intel Agilex 7 FPGAs Other Supported Intel FPGAs
tx_os
  • 1 - TMDS mode (1 GBPS < rate ≤ 6 Gbps)
  • 2 - TMDS mode (rate ≤ 1 Gbps)
  • 3 - FRL mode
  • 0 - FRL mode
  • 1 - TMDS mode (1 GBPS < rate ≤ 6 Gbps)
  • 2 - TMDS mode (rate ≤ 1 Gbps)
Core video out FRL/TMDS mode: 80b FRL/TMDS mode: 40b
Inner core video out
  • FRL mode: 40b
  • TMDS mode: 20b