HDMI Intel® FPGA IP User Guide

ID 683798
Date 3/03/2023

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Document Table of Contents

6.1.8. Status and Control Data Channel (SCDC) Interface

For applications using the features in HDMI 2.0b onwards, the core provides a memory slave port to the SCDC registers.

This memory slave port connects to an I2C slave component. The TMDS_Bit_clock_Ratio output from the SCDC interface indicates when the core requires the TMDS Bit Rate/TMDS Clock Rate ratio of 40. This bit is also stored in its corresponding field in the SCDC registers.

The HDMI 2.0b Specification requires the core to respond to the presence of the 5V input from the connector and the state of the HPD signal. The 5V input and HPD signal are used in the register mechanism updates. The signals are synchronous to the i2c_clk clock domain. You must create a 100-ms delay on the HPD signal externally to the core.

For more information about the Status and Control Data Channel, you may refer to HDMI 2.0b Specification Chapter 10.4. You can obtain the address map for the registers in the HDMI 2.0b Specification.