HDMI Intel® FPGA IP User Guide

ID 683798
Date 7/29/2022
Public
Document Table of Contents

9.1.1.35. SCDC_FRL_CONTROL (0x031)

Table 98.  SCDC_FRL_CONTROL (0x031)
Name Bit(s) Access Description Reset
SCDC frl pattern 31:16 RW

Indicates the link training pattern option that each lane on the TX core transmits.

scdc_frl_pattern[3:0]: Link training pattern option for lane 0

scdc_frl_pattern[7:4]: Link training pattern option for lane 1

scdc_frl_pattern[11:8]: Link training pattern option for lane 2

scdc_frl_pattern[15:12]: Link training pattern option for lane 3

Link training pattern options:

0x0: No link training pattern

0x1: All 1s pattern

0x2: All 0s pattern

0x3: Nyquist clock pattern

0x4: TxFFE Compliance Test Pattern

0x5: LFSR

00x6: LFSR

10x7: LFSR

20x8: LFSR 3

0x0
reserved 15:5 - - -
SCDC FRL rate 4:1 RW

Specifies the FRL rate (link rate and number of lanes) for HDMI Tx.

0x0: Disable FRL

0x1: Fixed rate link at 3 Gbps per lane on 3 lanes

0x2: Fixed rate link at 6 Gbps per lane on 3 lanes

0x3: Fixed rate link at 6 Gbps per lane on 4 lanes

0x4: Fixed rate link at 8 Gbps per lane on 4 lanes

0x5: Fixed rate link at 10 Gbps per lane on 4 lanes

0x6: Fixed rate link at 12 Gbps per lane on 4 lanes

0x0
SCDC FRL start 0 RW When set to 1, HDMI TX core transmits normal video data.

When set to 0, HDMI TX core transmits link training pattern data.

0x0

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