5.4. Link Training Procedure
Instead, the Nios® II software manages the link training process, which is demonstrated in the Intel® Arria® 10, Intel® Stratix® 10, and Intel® Agilex™ F-tile FRL design example.
Implement the link training external to the HDMI TX core according to the TX link training flow diagram shown below. The HDMI TX core generates different link training patterns on each lane based on your input through the scdc_frl_pattern port when scdc_frl_start is deasserted. When scdc_frl_start is asserted, the source core generates normal video.
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