- 4.1. HDMI Hardware Design Examples for Intel Arria 10, Intel Cyclone 10 GX, Intel Stratix 10, and Intel® Agilex™ F-tile Devices
5.1.9. HDCP 1.4 TX Architecture
- Control and Status Registers Layer
- Authentication Layer
- Video Stream and Auxiliary Layer
The Nios II processor typically drives the HDCP 1.4 TX core. The processor implements the authentication protocol. The processor accesses the IP through the Control and Status Port using Avalon Memory Mapped (Avalon-MM) interface.
The HDCP specifications requires the HDCP 1.4 TX core to be programmed with the DCP-issued production keys – Device Private Keys (Akeys) and Key Selection Vector (Aksv). The IP retrieves the key from the on-chip memory externally to the core through the HDCP Key Port. The on-chip memory must store the key data in the arrangement in the table below.
When authenticating with the HDCP 1.4 repeater device, the HDCP 1.4 TX core must perform the second part of the authentication protocol. This second part corresponds to the computation of the SHA-1 hash digest for all downstream device KSVs which are written to the registers in Control and Status Register Layer using the Control and Status Port (Avalon-MM).
The Video Stream and Auxiliary layer receives audio and video content over its Video and Aux Data Input Port, and performs the encryption operation. The Video Stream and Auxiliary Layer detects the Encryption Status Signaling (ESS) provided by the HDMI TX core to determine when to encrypt frames.
You can use the HDCP 1.4 registers to customize your design configurations. The HDCP 1.4 TX core supports full handshaking mechanism for authentication. Every issued command should be followed by polling of the assertion of its corresponding status bit before proceeding to issuing the next command. The value of AUTH_CMD must be in one-hot format that only one bit can be set at a time.
|5||GO_V||Set to 1 to compute V and compare against V’ during authentication with repeater. Self-cleared.|
|3||GEN_RI||Set to 1 to generate and receive R0 during authentication exchange or Ri during link integrity verification. Ri-Ri’ comparison should be performed by Nios® II processor. Self-cleared.|
|2||GO_KM||Set to 1 to compute master key (km). Self-cleared.|
|1||GEN_AKSV||Set to 1 to request and receive Aksv. Self-cleared.|
|0||GEN_AN||Set to 1 to generate and receive new true random An. Self-cleared.|
Write messages (in byte) from receiver in burst mode.
|0x02||AUTH_STATUS||RO||0x00000000||31||KM_OK||Asserted by the core to indicate the received Bksv is valid. Poll KM_DONE until it is set before reading KM_OK.|
|30||V_OK||Asserted by the core to indicate V-V’ comparison is passed. Poll V_DONE until it is set before reading V_OK.|
|5||V_DONE||Asserted by the core when V is generated. Self-cleared upon next GO_V is set.|
|3||RI_DONE||Asserted by the core when Ri is generated. Self-cleared upon next GEN_RI is set.|
|2||KM_DONE||Asserted by the core when Km is generated. Self-cleared upon next GO_KM is set.|
|1||AKSV_DONE||Asserted by the core when Aksv is ready to be read from MSGDATAOUT. Self-cleared upon next GEN_AKSV is set.|
|0||AN_DONE||Asserted by the core when new random An is generated and ready to be read from MSGDATAOUT. Self-cleared upon next GEN_AN is set.|
Read messages (in byte) from the IP in burst mode.
|0||HDCP_ENABLE||Set to 1 to enable HDCP 1.4 encryption. Set to 0 if HDCP 1.4 encryption is not required especially when it is in unauthenticated state.|
|1||REPEATER||Downstream repeater capability. Write bit 6 (REPEATER) of Bcaps received from downstream to this offset.|
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