HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.2.2.4. VIDEO_MODE_CONTROL (0x54)

Table 103.  VIDEO_MODE_CONTROL (0x54)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Interlaced 0 RW

Set to 1 for interlaced video.

Set to 0 for progressive video.

0x0

Did you find the information on this page useful?

Characters remaining:

Feedback Message