HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

4.3.1.11. Transceiver PHY Reset Controller

The Transceiver PHY Reset Controller IP core ensures a reliable initialization of the RX and TX transceivers.

The reset controller has separate reset controls per channel to handle synchronization of reset inputs, lagging of PLL locked status, and automatic or manual reset recovery mode.

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