HDMI Intel® FPGA IP User Guide

ID 683798
Date 7/29/2022
Public
Document Table of Contents

9.1.1.3. IRQ_MASK (0x02)

Table 67.  IRQ_MASK (0x02)
Name Bit(s) Access Description Reset
Reserved 31:4 - - -
Video overflow mask 3 RW Mask the video overflow input interrupt 0x0
Hotplugdetect mask 2 RW Mask the hotplug detect (HPD) input interrupt 0x0
Reserved 1:0 - - -

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