HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.2.2.2. VIDEO_MODE_MATCH (0x51)

Table 101.  VIDEO_MODE_MATCH (0x51)
Name Bit(s) Access Description Reset
Video mode match 31:0 RO Before any user specified mode is matched, this register reads back 0 indicating the default values are selected. Once a match has been made,the register reads back 0x1. 0x0

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