HDMI Intel® FPGA IP User Guide

ID 683798
Date 3/03/2023

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6.1.5. Sink Video Resampler

The video resampler consists of a gearbox and a dual-clock FIFO (DCFIFO).
The gearbox converts 8-bpc data to 8-, 10-, 12- or 16-bpc data based on the current color depth. The GCP conveys the color depth (bpp) information.
Figure 53. Sink Resampler Signal Flow Diagram
The resampler adheres to the recommended phase count method described in HDMI 1.4b Specification Section 6.5.
  • To keep the source and sink resamples synchronized, the source must send the packing-phase (pp) value to the sink during the vertical blanking phase, using the general control packet.
  • The pp corresponds to the phase of the last pixel in the last active video line.
  • The phase-counter logic compares its own pp value to the pp value received in the general control packet and slips the phase count if the two pp values do not agree.

The output from the resampler is fixed at 16 bpc. When the resampler operates in lower color depths, the low order bits are zero. The pixel data output format across color space are are described in Figure 10-12.