HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.1.1.12. VSI_PACKET_DATA0 (0x0F)

Refer to HDMI Specification 1.4b Section 8.2.3 HDMI Vendor Specific InfoFrame for the details of each field.
Table 76.  VSI_PACKET_DATA0 (0x0F)
Name Bit(s) Access Description Reset
VSI packet byte3 31:24 RW VSI packet data byte 3.

24 bit IEEE Registration Identifier.

0x0
VSI packet byte2 23:16 RW VSI packet data byte 2.

24 bit IEEE Registration Identifier.

0x0
VSI packet byte1 15:8 RW VSI packet data byte 1.

24 bit IEEE Registration Identifier.

0x0
VSI packet byte0 7:0 RW VSI packet data byte 0.

Checksum.

0x0

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