HDMI Intel® FPGA IP User Guide

ID 683798
Date 7/29/2022
Public
Document Table of Contents

9.3.1.12. USER_BUFFER_STATUS_CONTROL (0x11)

Table 132.  USER_BUFFER_STATUS_CONTROL (0x11)
Name Bit Access Description Reset
reserved 31:24 - - -
Buffer flush 4 WO Empty the data buffer. 0x0
Buffer full 3 RO Indicates that the data buffer is full. 0x0
Buffer empty 2 RO Indicates that the data buffer is empty. 0x0
Last 1 RO Indicates that data word to be read is the last in the current packet 0x0
Valid 0 RO Indicates that data is present in the buffer 0x0

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