22.214.171.124. PLL Reconfig Intel FPGA IP Core
Use the IP core to update the output clock frequency, PLL bandwidth in real-time, without reconfiguring the entire FPGA.
You can run this IP core at 100 MHz in Stratix V devices. In Arria V devices, you need to run at 75 MHz for timing closure. To simplify clocking in Arria V devices, the entire management clock domain is capped at 75 MHz.