HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9. Registers

HDMI Source and Sink controller registers consists of 3 main categories. You can use these categories to configure and read status for:
  • TX/RX Core functionality
  • TX AXI4-stream to clocked video converter or RX clocked video to AXI4-stream converter (optional)
  • TX I2C Master for DDC interface or RX EDID RAM

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