HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.4.2.9. CONTROL (0x64)

Table 158.  CONTROL (0x64)
Name Bit(s) Access Description Reset
Reserved 31:1 - - -
Go 0 WO Setting this bit to 1 causes the CV2AXI core to start data output on the next video frame boundary. 0x0

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