HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

5.1.7.3. Source HDMI Vendor Specific InfoFrame (VSI)

Table 26.  Source HDMI Vendor Specific InfoFrame Bit-FieldsThe table below lists the bit-fields for VSI (as described in HDMI 1.4b Specification Section 8.2.3).

The signal bundle is clocked by ls_clk.

Note: For the HDMI Forum-VSI InfoFrame (HF-VSIF) transmission, use external VSI by asserting control bit to 1 and send the data through the Auxiliary Data Port.
Bit-field Name Description Default Value
4:0 Length Length of HDMI VSI payload 5’h06
12:5 Checksum Checksum 8’h69
36:13 IEEE 24-bit IEEE registration identifier (0×000C03) 24’h000C03
41:37 Reserved Reserved (0) 5’h00
44:42 HDMI_Video_Format Structure of extended video formats exclusively defined in HDMI 1.4b Specification 3’h0
52:45 HDMI_VIC or 3D_Structure
  • If HDMI_Video_Format = 3’h1, [52:45] = HDMI proprietary video format identification code
  • If HDMI_Video_Format = 3’h2, [52:49] = 3D_Structure and [48:45] = Reserved (0)
8’h00
56:53 Reserved Reserved (0) 4’h00
60:57 3D_Ext_Data 3D extended data 4’h0
61 Control Disables the core from inserting the InfoFrame packet.
  • 1: The core does not insert info_vsi[60:0]. The VSI InfoFrame packet on the Auxiliary Data Port passes through.
  • 0: The core inserts info_vsi[60:0] when there is a non-zero bit. The core sends default values when all bits are zero. The core filters the VSI InfoFrame packet on the Auxiliary Data Port.

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