HDMI Intel® FPGA IP User Guide

ID 683798
Date 1/30/2023
Public
Document Table of Contents

9.3.1.28. SCDC_FRL_CONTROL (0x2F)

Table 148.  SCDC_FRL_CONTROL (0x2F)
Name Bit Access Description Reset
SCDC FRL LTP request 31:16 RW

Write to the SCDC status flags 0x41 and 0x42 to request the source to transmit specific link training pattern. Set scdc_frl_ltp_req[15:0] 0x0000 to pass the link training process.

Bit [15:12]: Link training pattern forlane 3 (SCDC status flag 0x42 bit[7:4])

Bit [11:8]: Link training pattern for lane 2 (SCDC status flag 0x42 bit[3:0])

Bit [7:4]: Link training pattern for lane 1 (SCDC status flag 0x41 bit[7:4])

Bit [3:0]: Link training pattern for lane 0 (SCDC status flag 0x41bit[3:0])

By default this register is disabled. Sink always request link training pattern 0x5678. To enable other link training pattern please contact Sale.

Sink does not support FFE. Pattern 0xEEEE are not supported.

Sink link training process does not automatically change to other FRL rates.

Pattern 0xFFFF are not supported.

0x0
SCDC FRL source test config 15:8 RW

Configure the Source Test Configuration register (SCDC register 0x35)

Bit 7 : FRL_Max

Bit 6: SDC_FRL_Max

Bit 5: FLT_no_timeout

Bit 4: Reserved

Bit 3: TxFFE_No_FFE

Bit 2: TxFFE_De_Emphasis_only

Bit 1: TxFFE_Pre_Shoot_Only

Bit 0: Reserved

For more information about these bits, refer to the 10.4.1.6.1 Source Test Configuration Request section of the HDMI 2.1 Specifications.

0x0
SCDC FRL FLT ready 0 RW

Set this bit to 1 when the HDMI RX core is ready for the link training process.

When asserted, the FLT_Ready bit in the SCDC status flag 0x40 bit6 is set to 1, the FRL start flag is cleared, and the FLT update flag is set for the link training process.

0x0

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