HDMI Intel® FPGA IP User Guide

ID 683798
Date 3/03/2023
Public
Document Table of Contents

5.1.2. Source Video Resampler

The video resampler consists of a dual-clock FIFO (DCFIFO) and a gearbox.

The gearbox converts data of 8, 10, 12, or 16 bits per component to 8-bit per component data based on the current color depth. The General Control Packet (GCP) conveys the color depth information.

Figure 16. Source Video Resampler Signal Flow DiagramThe figure below shows the components of the video resampler and the signal flow between these components.
The resampler adheres to the recommended phase encoding method described in HDMI 1.4b Specification Section 6.5.
  • The phase counter must register the last pixel packing-phase (pp) of the last pixel of the last active line.
  • The core then transmits the pp value to the attached sink device in the GCP for packing synchronization.

The HDMI cable may send across four different pixel encodings: RGB 4:4:4, YCbCr 4:4:4, and YCbCr 4:2:2 (as described in HDMI 1.4b Specification Section 6.5), and YCbCr 4:2:0 (as described in HDMI 2.0b Specification Section 7.1).

Figure 17. Pixel Data Input Format RGB/YCbCr 4:4:4The figure below shows the RGB/YCbCr 4:4:4 color space pixel bit-field mappings per symbol. When the actual color depth is below 16 bpc, the unused LSBs are set to zero.
Figure 18. Pixel Data Input Format YCbCr 4:2:2 The figure below shows the YCbCr 4:2:2 color space pixel bit-field mappings per symbol. As with 4:4:4 color space, the unused LSBs are set to zero. YCbCr422 is transmitted using 24bpp (8 bpc) HDMI transport. You should set the GCP[3:0] to 0x0 or 0x4 for 24bpp (8 bpc).

The higher order 8 bits of the Y samples are mapped to the 8 bits of Channel 1 and the lower order 4 bits are mapped to the lower order 4 bits of Channel 0. If you are using fewer than 12 bits, leave the valid bits left-justified with zeros padding the bits below the least significant bit.

The first pixel transmitted within a Video Data Period contains three components, Y0, Cb0 and Cr0. The Y0 and Cb0 components are transmitted during the first pixel period while Cr0 is transmitted during the second pixel period. This second pixel period also contains the only component for the second pixel, Y1. In this way, the link carries one Cb sample for every two pixels and one Cr sample for every two pixels. These two components (Cb and Cr) are multiplexed onto the same signal paths on the link.

Figure 19. Pixel Data Input Format YCbCr 4:2:0 The figure shows the YCbCr 4:2:0 color space pixel bit-field mappings. As with 4:4:4 color space, the unused LSBs are set to zero.

The two horizontally successive 8-bit Y components are transmitted in TMDS Channels 1 and 2, in that order. The 8-bit Cb or Cr components are transmitted alternately in TMDS Channel 0, line by line.

For even lines starting with line 0:

  • vid_data[47:32] always transfer the Yn+1 component
  • vid_data[31:16] always transfer the Yn component
  • vid_data[15:0] always transfer the Cbn component

For odd lines:

  • vid_data[47:32] always transfer the Yn+1 component
  • vid_data[31:16] always transfer the Yn component
  • vid_data[15:0] always transfer the Crn component

The frequency of vid_clk must be halved when YCbCr 4:2:0 is used, because two pixels are fed into a single clock cycle.

Figure 20. YCbCr 4:2:0 Transport Using 1 Symbol Per Clock Mode The figure below shows the YCbCr 4:2:0 transmission when the core operates in 1 symbol per clock mode.

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