HDMI Intel® FPGA IP User Guide

ID 683798
Date 7/29/2022
Public
Document Table of Contents

9.4.2.3. F0_ACTIVE_LINE_COUNT (0x53)

Table 152.  F0_ACTIVE_LINE_COUNT (0x53)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F0 active line count 15:0 RO The detected line count of the interlaced video field 0 or progressive video excluding blanking. 0x0

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