HDMI Intel® FPGA IP User Guide

ID 683798
Date 3/03/2023
Public
Document Table of Contents

9.2.2.18. VIDEO_MODE_F0_VERTICAL_RISING (0x62)

Table 118.  VIDEO_MODE_F0_VERTICAL_RISING (0x62)
Name Bit(s) Access Description Reset
Reserved 31:16 - - -
F0 vertical rising 15:0 RW Specifies the line number given to the start of field 0's vertical blanking. 0x0

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