Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

5.4.6. Guideline: VREF Pin Restrictions

For the Cyclone® V devices, consider the following VREF pins guidelines:

  • You cannot assign shared VREF pins as LVDS or external memory interface pins.
  • SSTL, HSTL, and HSUL I/O standards do not support shared VREF pins. For example, if a particular B1p or B1n pin is a shared VREF pin, the corresponding B1p/B1n pin pair do not have LVDS transmitter support.
  • You must perform signal integrity analysis using your board design when using a shared VREF pin to determine the FMAX for your system.

For more information about pin capacitance of the VREF pins, refer to the device datasheet.