4.2.6. PLL External Clock I/O Pins
All Cyclone® V external clock outputs for corner fractional PLLs (that are not from the PLL strips) are dual-purpose clock I/O pins. Two external clock output pins associated with each corner fractional PLL are organized as one of the following combinations:
- Two single-ended clock outputs
- One differential clock output
- Two single-ended clock outputs and one single-ended clock input in the I/O driver feedback for zero delay buffer (ZDB) mode support
- One single-ended clock output and one single-ended feedback input for single-ended external feedback (EFB) mode support
- One differential clock output and one differential feedback input for differential EFB support
The following figure shows that any of the output counters ( C[0..8]) or the M counter on the PLLs can feed the dedicated external clock outputs. Therefore, one counter or frequency can drive all output pins available from a given PLL.
Each pin of a single-ended output pair can be either in-phase or 180° out-of-phase. To implement the 180° out-of-phase pin in a pin pair, the Intel® Quartus® Prime software places a NOT gate in the design into the IOE.
The clock output pin pairs support the following I/O standards:
- Same I/O standard for the pin pairs
- Differential high-speed transceiver logic (HSTL)
- Differential SSTL
Cyclone® V PLLs can drive out to any regular I/O pin through the GCLK or RCLK network. You can also use the external clock output pins as user I/O pins if you do not require external PLL clocking.
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