126.96.36.199. External Feedback Mode
In EFB mode, the output of the M counter (fbout) feeds back to the PLL fbin input (using a trace on the board) and becomes part of the feedback loop.
One of the dual-purpose external clock outputs becomes the fbin input pin in this mode. The external feedback input pin, fbin is phase-aligned with the clock input pin. Aligning these clocks allows you to remove clock delay and skew between devices.
When using EFB mode, you must use the same I/O standard on the input clock, feedback input, and clock outputs.
This mode is supported only on the corner fractional PLLs. For Cyclone® V E A2 and A4 devices, and Cyclone® V GX C3 device, EFB mode is supported only on the left corner fractional PLLs.
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