Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

5.14.4. Receiver Skew Margin for LVDS Mode

In LVDS mode, use RSKM, TCCS, and sampling window (SW) specifications for high-speed source-synchronous differential signals in the receiver data path.

The following equation expresses the relationship between RSKM, TCCS, and SW.

Figure 117. RSKM Equation

Conventions used for the equation:

  • RSKM—the timing margin between the receiver’s clock input and the data input sampling window.
  • Time unit interval (TUI)—time period of the serial data.
  • SW—the period of time that the input data must be stable to ensure that data is successfully sampled by the LVDS receiver. The SW is a device property and varies with device speed grade.
  • TCCS—the timing difference between the fastest and the slowest output edges, including tCO variation and clock skew, across channels driven by the same PLL. The clock is included in the TCCS measurement.

You must calculate the RSKM value to decide whether the LVDS receiver can sample the data properly or not, given the data rate and device. A positive RSKM value indicates that the LVDS receiver can sample the data properly, whereas a negative RSKM indicates that it cannot sample the data properly.

The following figure shows the relationship between the RSKM, TCCS, and the SW of the receiver.

Figure 118. Differential High-Speed Timing Diagram and Timing Budget for LVDS Mode

For LVDS receivers, the Intel® Quartus® Prime software provides an RSKM report showing the SW, TUI, and RSKM values for non-DPA LVDS mode:

  • You can generate the RSKM report by executing the report_RSKM command in the Timing Analyzer. You can find the RSKM report in the Intel® Quartus® Prime compilation report in the Timing Analyzer section.
  • To obtain the RSKM value, assign the input delay to the LVDS receiver through the constraints menu of the Timing Analyzer. The input delay is determined according to the data arrival time at the LVDS receiver port, with respect to the reference clock.
  • If you set the input delay in the settings parameters for the Set Input Delay option, set the clock name to the clock that reference the source synchronous clock that feeds the LVDS receiver.
  • If you do not set any input delay in the Timing Analyzer, the receiver channel-to-channel skew defaults to zero.
  • You can also directly set the input delay in a Synopsys Design Constraint file (.sdc) using the set_input_delay command.