Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

7.2. MSEL Pin Settings

To select a configuration scheme, hardwire the MSEL pins to VCCPGM or GND without pull-up or pull-down resistors.

Note: Altera recommends connecting the MSEL pins directly to VCCPGM or GND. Driving the MSEL pins from a microprocessor or another controlling device may not guarantee the VIL or VIH of the MSEL pins. The VIL or VIH of the MSEL pins must be maintained throughout configuration stages.
Table 93.  MSEL Pin Settings for Each Configuration Scheme of Cyclone V Devices
Configuration Scheme Compression Feature Design Security Feature VCCPGM (V) Power-On Reset (POR) Delay Valid MSEL[4..0]
FPP x8 Disabled Disabled 1.8/2.5/3.0/3.3 Fast 10100
Standard 11000
Disabled Enabled 1.8/2.5/3.0/3.3 Fast 10101
Standard 11001
Enabled Enabled/Disabled 1.8/2.5/3.0/3.3 Fast 10110
Standard 11010
FPP x16 20 Disabled Disabled 1.8/2.5/3.0/3.3 Fast 00000
Standard 00100
Disabled Enabled 1.8/2.5/3.0/3.3 Fast 00001
Standard 00101
Enabled Enabled/Disabled 1.8/2.5/3.0/3.3 Fast 00010
Standard 00110
PS Enabled/Disabled Enabled/Disabled 1.8/2.5/3.0/3.3 Fast 10000
Standard 10001
AS (x1 and x4) Enabled/Disabled Enabled/Disabled 3.0/3.3 Fast 10010
Standard 10011
JTAG-based configuration Disabled Disabled Use any valid MSEL pin settings above
Note: You must also select the configuration scheme in the Configuration page of the Device and Pin Options dialog box in the Intel® Quartus® Prime software. Based on your selection, the option bit in the programming file is set accordingly.
20 For configuration with HPS in SoC FPGA devices, refer to the FPGA Manager for the related MSEL pin settings.