5.4.2. PLLs and Clocking
The Cyclone® V device family supports fractional PLLs on each side of the device. You can use fractional PLLs to reduce the number of oscillators and the clock pins used in the FPGA by synthesizing multiple clock frequencies from a single reference clock source.
The corner fractional PLLs can drive the LVDS receiver and driver channels. However, the clock tree network cannot cross over to different I/O regions. For example, the top left corner fractional PLL cannot cross over to drive the LVDS receiver and driver channels on the top right I/O bank. The Intel® Quartus® Prime compiler automatically checks the design and issues an error message if the guidelines are not followed.
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