Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents Guideline: Reference Clock Restriction for LVDS Application

You must use the dedicated reference clock pin of the same I/O bank used by the data channel. For I/O banks without a dedicated reference clock pin, use the reference clock pin in the I/O bank listed in the following table.
Table 36.  Reference Clock Pin for I/O Bank Without Dedicated Reference Clock Pin
Device Variant Member Code Data Channel I/O Bank Reference Clock Pin I/O Bank
Cyclone V E A2, A4 Banks using bottom right PLL 4A
Banks using bottom left PLL 3B
Banks using top right PLL 7A
Banks using top left PLL 8A
A5, A7, A9 3A 3B
5A 5B
Cyclone V GX C3, C4, C7, C9 3A 3B
5A 5B
C5 3A 3B
5A 5B
7A 8A
Cyclone V GT D5, D9 3A 3B
5A 5B
D7 3A 3B
Cyclone V SE A2, A4 3A 3B
A5, A6 5A 5B
Cyclone V SX C2, C4 3A 3B
C5, C6 5A 5B
Cyclone V ST D5, D6 5A 5B