Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents Transmitter Clocking

The fractional PLL generates the parallel clocks (rx_outclock and tx_outclock), the load enable (LVDS_LOAD_EN) signal and the diffioclk signal (the clock running at serial data rate) that clocks the load and shift registers. You can statically set the serialization factor to x4, x5, x6, x7, x8, x9, or x10 using the Intel® Quartus® Prime software. The load enable signal is derived from the serialization factor setting.

You can configure any Cyclone® V transmitter data channel to generate a source-synchronous transmitter clock output. This flexibility allows the placement of the output clock near the data outputs to simplify board layout and reduce clock-to-data skew.

Different applications often require specific clock-to-data alignments or specific data-rate-to-clock-rate factors. You can specify these settings statically in the Intel® Quartus® Prime IP Catalog:

  • The transmitter can output a clock signal at the same rate as the data—with a maximum output clock frequency that each speed grade of the device supports.
  • You can divide the output clock by a factor of 1, 2, 4, 6, 8, or 10, depending on the serialization factor.
  • You can set the phase of the clock in relation to the data using internal PLL option of the ALTLVDS IP core. The fractional PLLs provide additional support for other phase shifts in 45° increments.

The following figure shows the transmitter in clock output mode. In clock output mode, you can use an LVDS channel as a clock output channel.

Figure 107. Transmitter in Clock Output Mode