Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 7/05/2022
Document Table of Contents LVDS Receiver Mode

Input serial data is registered at the rising edge of the serial LVDS_diffioclk clock that is produced by the left and right PLLs.

You can select the rising edge option with the Intel® Quartus® Prime IP Catalog. The LVDS_diffioclk clock that is generated by the left and right PLLs clocks the data realignment and deserializer blocks.

The following figure shows the LVDS datapath block diagram. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.

Figure 113. Receiver Data Path in LVDS Mode

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