Visible to Intel only — GUID: sam1403478287661
Ixiasoft
Visible to Intel only — GUID: sam1403478287661
Ixiasoft
5.13.2.1. LVDS Receiver Mode
Input serial data is registered at the rising edge of the serial LVDS_diffioclk clock that is produced by the left and right PLLs.
You can select the rising edge option with the Intel® Quartus® Prime IP Catalog. The LVDS_diffioclk clock that is generated by the left and right PLLs clocks the data realignment and deserializer blocks.
The following figure shows the LVDS datapath block diagram. In SDR and DDR modes, the data width from the IOE is 1 and 2 bits, respectively.
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