Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

5.13.3. Receiver Clocking for Cyclone® V Devices

The fractional PLL receives the external clock input and generates different phases of the same clock.

The physical medium connecting the transmitter and receiver LVDS channels may introduce skew between the serial data and the source-synchronous clock. The instantaneous skew between each LVDS channel and the clock also varies with the jitter on the data and clock signals as seen by the receiver.

LVDS mode allows you to statically select the optimal phase between the source synchronous clock and the received serial data to compensate skew.