184.108.40.206. Manual Clock Switchover
In manual clock switchover mode, the extswitch signal controls whether inclk0 or inclk1 is selected as the input clock to the PLL. By default, inclk0 is selected.
A clock switchover event is initiated when the extswitch signal transitions from logic low to logic high, and being held high for at least three inclk cycles.
You must bring the extswitch signal back low again for PLL to re-gain lock. If you do not require another switchover event, you can leave the extswitch signal in a logic low state.
Pulsing the extswitch signal high for at least three inclk cycles performs another switchover event.
If inclk0 and inclk1 are different frequencies and are always running, the extswitch signal minimum high time must be greater than or equal to three of the slower frequency inclk0 and inclk1 cycles.
You can delay the clock switchover action by specifying the switchover delay in the ALTERA_PLL IP core. When you specify the switchover delay, the extswitch signal must be held high for at least three inclk cycles plus the number of the delay cycles that has been specified to initiate a clock switchover.
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