Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 7/05/2022
Document Table of Contents

1.3. Logic Array Blocks and Adaptive Logic Modules in Cyclone® V Devices Revision History

Date Version Changes
August 2016 2016.08.24 Added description on clock source in the LAB Control Signals section.
December 2015 2015.12.21 Changed instances of Quartus II to Quartus Prime.
January 2014 2014.01.10 Added multiplexers for the bypass paths and register outputs in the following diagrams:
  • ALM High-Level Block Diagram for Cyclone® V Devices
  • Template for Supported 7-Input Functions in Extended LUT Mode for Cyclone® V Devices
  • ALM in Arithmetic Mode for Cyclone® V Devices
  • ALM in Shared Arithmetic Mode for Cyclone® V Devices
May 2013 2013.05.06
  • Added link to the known document issues in the Knowledge Base.
  • Removed register chain outputs information in ALM output section.
  • Removed reg_chain_in and reg_chain_out ports in ALM high-level block diagram and ALM connection details diagram.
December 2012 2012.12.28 Reorganized content and updated template.
June 2012 2.0

Updated for the Quartus II software v12.0 release:

  • Restructured chapter.
  • Updated Figure 1–6.
November 2011 1.1 Minor text edits.
October 2011 1.0 Initial release.

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