7.8.2. Evaluating Data Setup and Hold Timing Slack in AS Configuration
Follow the guideline below to evaluate and ensure the setup time, tDSU and hold time, tDH meets the requirements explained in the Cyclone® V device datasheets. While evaluating the tDSU and tDH slack in your system, you can also use the equations to estimate the trace length for the DCLK and DATA[3..0] lines on your system.
The data setup timing slack must be equal or larger than the minimum data setup time, tDSU
tDCLK – (tBT_DCLK + tCLQV + tBT_DATA) ≥ tDSU
The hold timing slack must be equal or larger than the minimum data hold time, tDH:
tBT_DCLK + tCLQX + tBT_DATA ≥ tDH
- tDCLK = Period for a DCLK cycle
- tBT_DCLK = Board trace propagation delay for DCLK from FPGA to EPCQ-A
- tCLQV = Clock low to output valid
- tCLQX = Output hold time
- tBT_DATA = Board trace propagation delay for Data from EPCQ-A to FPGA
- tDSU = Minimum data setup time required by FPGA
- tDH = Minimum data hold time required by FPGA
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