Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents Altera_PLL Signal Interface with ALTLVDS IP Core

Table 37.  Signal Interface Between Altera_PLL and ALTLVDS IP Cores This table lists the signal interface between the output ports of the Altera_PLL IP core and the input ports of the ALTLVDS transmitter and receiver. As an example, the table lists the serial clock output, load enable output, and parallel clock output generated on ports outclk0, outclk1, and outclk2, along with the locked signal of the Altera_PLL instance. You can choose any of the PLL output clock ports to generate the interface clocks.
From the Altera_PLL IP Core To the ALTLVDS Transmitter To the ALTLVDS Receiver

Serial clock output (outclk0)

The serial clock output (outclk0) can only drive tx_inclock on the ALTLVDS transmitter, and rx_inclock on the ALTLVDS receiver. This clock cannot drive the core logic.

tx_inclock (serial clock input to the transmitter)

rx_inclock (serial clock input)

Load enable output (outclk1)

tx_enable (load enable to the transmitter)

rx_enable (load enable for the deserializer)

Parallel clock output (outclk2)

Parallel clock used inside the transmitter core logic in the FPGA fabric

Parallel clock used inside the receiver core logic in the FPGA fabric


pll_areset (asynchronous PLL reset port)

The pll_areset signal is automatically enabled for the LVDS receiver in external PLL mode. This signal does not exist for LVDS transmitter instantiation when the external PLL option is enabled.

Note: With soft SERDES, a different clocking requirement is needed.