Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 7/05/2022
Public
Document Table of Contents

9.1.2. Supported JTAG Instruction

Table 113.  JTAG Instructions Supported by Cyclone® V Devices
JTAG Instruction Instruction Code Description
SAMPLE / PRELOAD 00 0000 0101
  • Allows you to capture and examine a snapshot of signals at the device pins during normal device operation and permits an initial data pattern to be an output at the device pins.
  • Use this instruction to preload the test data into the update registers before loading the EXTEST instruction.
  • Used by the Signal Tap II Embedded Logic Analyzer.
EXTEST 00 0000 1111
  • Allows you to test the external circuit and board-level interconnects by forcing a test pattern at the output pins, and capturing the test results at the input pins. Forcing known logic high and low levels on output pins allows you to detect opens and shorts at the pins of any device in the scan chain.
  • The high-impedance state of EXTEST is overridden by bus hold and weak pull-up resistor features.
BYPASS 11 1111 1111 Places the 1-bit bypass register between the TDI and TDO pins. During normal device operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices.
USERCODE 00 0000 0111
  • Examines the user electronic signature (UES) within the devices along a JTAG chain.
  • Selects the 32-bit USERCODE register and places it between the TDI and TDO pins to allow serial shifting of USERCODE out of TDO.
  • The UES value is set to default value before configuration and is only user-defined after the device is configured.
IDCODE 00 0000 0110
  • Identifies the devices in a JTAG chain. If you select IDCODE, the device identification register is loaded with the 32-bit vendor-defined identification code.
  • Selects the IDCODE register and places it between the TDI and TDO pins to allow serial shifting of IDCODE out of TDO.
  • IDCODE is the default instruction at power up and in the TAP RESET state. Without loading any instructions, you can go to the SHIFT_DR state and shift out the JTAG device ID.
HIGHZ 00 0000 1011
  • Sets all user I/O pins to an inactive drive state.
  • Places the 1-bit bypass register between the TDI and TDO pins. During normal operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices while tri-stating all I/O pins until a new JTAG instruction is executed.
  • If you are testing the device after configuration, the programmable weak pull-up resistor or the bus hold feature overrides the HIGHZ value at the pin.
CLAMP 00 0000 1010
  • Places the 1-bit bypass register between the TDI and TDO pins. During normal operation, the 1-bit bypass register allows the BST data to pass synchronously through the selected devices to adjacent devices while holding the I/O pins to a state defined by the data in the boundary-scan register.
  • If you are testing the device after configuration, the programmable weak pull-up resistor or the bus hold feature overrides the CLAMP value at the pin. The CLAMP value is the value stored in the update register of the boundary-scan cell (BSC).
PULSE_NCONFIG 00 0000 0001 Emulates pulsing the nCONFIG pin low to trigger reconfiguration even though the physical pin is not affected.
CONFIG_IO 00 0000 1101 Allows I/O reconfiguration (after or during reconfigurations) through the JTAG ports using I/O configuration shift register (IOCSR) for JTAG testing. You can issue the CONFIG_IO instruction only after the nSTATUS pin goes high.
LOCK 01 1111 0000 Put the device in JTAG secure mode. In this mode, only BYPASS, SAMPLE/PRELOAD, EXTEST, IDCODE, SHIFT_EDERROR_REG , and UNLOCK instructions are supported. This instruction can only be accessed through JTAG core access in user mode. It cannot be accessed through external JTAG pins in test or user mode.
UNLOCK 11 0011 0001 Release the device from the JTAG secure mode to enable access to all other JTAG instructions. This instruction can only be accessed through JTAG core access in user mode. It cannot be accessed through external JTAG pins in test or user mode.
KEY_CLR_VREG 00 0010 1001 Clears the volatile key.
KEY_VERIFY 00 0001 0011 Verifies the non-volatile key has been cleared.
Note: If the device is in a reset state and the nCONFIG or nSTATUS signal is low, the device IDCODE might not be read correctly. To read the device IDCODE correctly, you must issue the IDCODE JTAG instruction only when the nCONFIG and nSTATUS signals are high.

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