Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents Normal Compensation Mode

An internal clock in normal compensation mode is phase-aligned to the input clock pin. The external clock output pin has a phase delay relative to the clock input pin if connected in this mode. The Intel® Quartus® Prime Timing Analyzer reports any phase difference between the two. In normal compensation mode, the delay introduced by the GCLK or RCLK network is fully compensated.

Figure 62. Example of Phase Relationship Between the PLL Clocks in Normal Compensation Mode