2.4. Embedded Memory Modes
|Memory Mode||M10K Support||MLAB Support||Description|
You can perform only one read or one write operation at a time.
Use the read enable port to control the RAM output ports behavior during a write operation:
|Simple dual-port RAM||Yes||Yes||
You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B.
|True dual-port RAM||Yes||—||
You can perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies.
You can use the memory blocks as a shift-register block to save logic cells and routing resources.
This is useful in DSP applications that require local data storage such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross- correlation functions. Traditionally, the local data storage is implemented with standard flip-flops that exhaust many logic cells for large shift registers.
The input data width (w), the length of the taps (m), and the number of taps (n) determine the size of a shift register (w × m × n). You can cascade memory blocks to implement larger shift registers.
You can use the memory blocks as ROM.
You can use the memory blocks as FIFO buffers. Use the SCFIFO and DCFIFO IP cores to implement single- and dual-clock asynchronous FIFO buffers in your design.
For designs with many small and shallow FIFO buffers, the MLABs are ideal for the FIFO mode. However, the MLABs do not support mixed-width FIFO mode.
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