Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

2.4. Embedded Memory Modes

To avoid corrupting the memory contents, do not violate the setup or hold time on any of the memory block input registers during read or write operations. This is applicable if you use the memory blocks in single-port RAM, simple dual-port RAM, true dual-port RAM, or ROM mode.
Table 9.  Memory Modes Supported in the Embedded Memory BlocksThis table lists and describes the memory modes that are supported in the Cyclone® V embedded memory blocks.
Memory Mode M10K Support MLAB Support Description
Single-port RAM Yes Yes

You can perform only one read or one write operation at a time.

Use the read enable port to control the RAM output ports behavior during a write operation:

  • To retain the previous values that are held during the most recent active read enable—create a read-enable port and perform the write operation with the read enable port deasserted.
  • To show the new data being written, the old data at that address, or a "Don't Care" value when read-during-write occurs at the same address location—do not create a read-enable signal, or activate the read enable during a write operation.
Simple dual-port RAM Yes Yes

You can simultaneously perform one read and one write operations to different locations where the write operation happens on port A and the read operation happens on port B.

True dual-port RAM Yes

You can perform any combination of two port operations: two reads, two writes, or one read and one write at two different clock frequencies.

Shift-register Yes Yes

You can use the memory blocks as a shift-register block to save logic cells and routing resources.

This is useful in DSP applications that require local data storage such as finite impulse response (FIR) filters, pseudo-random number generators, multi-channel filtering, and auto- and cross- correlation functions. Traditionally, the local data storage is implemented with standard flip-flops that exhaust many logic cells for large shift registers.

The input data width (w), the length of the taps (m), and the number of taps (n) determine the size of a shift register (w × m × n). You can cascade memory blocks to implement larger shift registers.

ROM Yes Yes

You can use the memory blocks as ROM.

  • Initialize the ROM contents of the memory blocks using a .mif or .hex.
  • The address lines of the ROM are registered on M10K blocks but can be unregistered on MLABs. However, the unregistered address line on MLABs is supported for simple dual-port RAM mode only.
  • The outputs can be registered or unregistered.
  • The output registers can be asynchronously cleared.
  • The ROM read operation is identical to the read operation in the single-port RAM configuration.
FIFO Yes Yes

You can use the memory blocks as FIFO buffers. Use the SCFIFO and DCFIFO IP cores to implement single- and dual-clock asynchronous FIFO buffers in your design.

For designs with many small and shallow FIFO buffers, the MLABs are ideal for the FIFO mode. However, the MLABs do not support mixed-width FIFO mode.