Cyclone V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 7/05/2022
Public
Document Table of Contents

5.8.1. Programmable Current Strength

You can use the programmable current strength to mitigate the effects of high signal attenuation that is caused by a long transmission line or a legacy backplane.

Table 50.  Programmable Current Strength Settings for Cyclone® V DevicesThe output buffer for each Cyclone® V device I/O pin has a programmable current strength control for the I/O standards listed in this table.
I/O Standard

IOH / IOL Current Strength Setting (mA)

(Default setting in bold)

Supported in HPS

(SoC Devices Only)

3.3 V LVTTL 16, 8, 4 Yes (except 16 mA)
3.3 V LVCMOS 2 Yes
3.0 V LVTTL 16, 12, 8, 4 Yes
3.0 V LVCMOS 16, 12, 8, 4 Yes
2.5 V LVCMOS 16, 12, 8, 4 Yes
1.8 V LVCMOS 12, 10, 8, 6, 4, 2 Yes
1.5 V LVCMOS 12, 10, 8, 6, 4, 2 Yes
1.2 V LVCMOS 8, 6, 4, 2
SSTL-2 Class I 12, 10, 8
SSTL-2 Class II 16
SSTL-18 Class I 12, 10, 8, 6, 4 Yes
SSTL-18 Class II 16 Yes
SSTL-15 Class I 12, 10, 8, 6, 4 Yes
SSTL-15 Class II 16 Yes
1.8 V HSTL Class I 12, 10, 8, 6, 4
1.8 V HSTL Class II 16
1.5 V HSTL Class I 12, 10, 8, 6, 4 Yes
1.5 V HSTL Class II 16 Yes
1.2 V HSTL Class I 12, 10, 8, 6, 4
1.2 V HSTL Class II 16
Note: Intel recommends that you perform IBIS or SPICE simulations to determine the best current strength setting for your specific application.

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