Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

6.4.3. DQS Phase-Shift Circuitry

The Cyclone® V DLL provides phase shift to the DQS pins on read transactions if the DQS pins are acting as input clocks or strobes to the FPGA.

The following figures show how the DLLs are connected to the DQS pins in the various Cyclone® V variants. The reference clock for each DLL may come from adjacent PLLs.

Note: The following figures show all possible connections for each device. For available pins and connections in each device package, refer to the device pin-out files.
Figure 120. DQS Pins and DLLs in Cyclone® V E (A2 and A4) Devices

Figure 121. DQS Pins and DLLs in Cyclone® V GX (C3) Devices

Figure 122. DQS Pins and DLLs in Cyclone® V E (A5, A7, and A9), GX (C4, C5, C7, and C9), GT (D5, D7, and D9) Devices

Figure 123. DQS Pins and DLLs in Cyclone® V SE (A2, A4, A5, and A6) Devices

Figure 124. DQS Pins and DLLs in Cyclone® V SX (C2, C4, C5, and C6) and ST (D5 and D6) Devices