Visible to Intel only — GUID: sam1403478698743
Ixiasoft
Visible to Intel only — GUID: sam1403478698743
Ixiasoft
6.4.8. Delay Chains
The Cyclone® V devices contain run-time adjustable delay chains in the I/O blocks and the DQS logic blocks. You can control the delay chain setting through the I/O or the DQS configuration block output.
Every I/O block contains a delay chain between the following elements:
- The output registers and output buffer
- The input buffer and input register
- The output enable and output buffer
- The R T OCT enable-control register and output buffer
You can bypass the DQS delay chain to achieve a 0° phase shift.
Each DQS logic block contains a delay chain after the dqsbusout output and another delay chain before the dqsenable input.
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