Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents Connection between Altera_PLL and ALTLVDS

Figure 76. LVDS Interface with the Altera_PLL IP CoreThis figure shows the connections between the Altera_PLL and ALTLVDS IP core.

When generating the Altera_PLL IP core, the Left/Right PLL option is configured to set up the PLL in LVDS mode. Instantiation of pll_areset is optional.

The rx_enable and rx_inclock input ports are not used and can be left unconnected.