Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

4.2. Cyclone® V PLLs

PLLs provide robust clock management and synthesis for device clock management, external system clock management, and high-speed I/O interfaces.

The Cyclone® V device family contains fractional PLLs that can function as fractional PLLs or integer PLLs. The output counters in Cyclone® V devices are dedicated to each fractional PLL that support integer or fractional frequency synthesis.

The Cyclone® V devices offer up to 8 fractional PLLs in the larger densities.

Table 24.  PLL Features in Cyclone® V Devices
Feature Support
Integer PLL Yes
Fractional PLL Yes
C output counters 9
M, N, C counter sizes 1 to 512
Dedicated external clock outputs 2 single-ended and 1 differential
Dedicated clock input pins 4 single-ended or 4 differential
External feedback input pin Single-ended or differential
Spread-spectrum input clock tracking Yes 5
Source synchronous compensation Yes
Direct compensation Yes
Normal compensation Yes
Zero-delay buffer compensation Yes
External feedback compensation Yes
LVDS compensation Yes
Phase shift resolution 78.125 ps 6
Programmable duty cycle Yes
Power down mode Yes
5 Provided input clock jitter is within input jitter tolerance specifications. The modulation frequency of the input clock is below the PLL bandwidth which is specified in the Fitter report.
6 The smallest phase shift is determined by the voltage-controlled oscillator (VCO) period divided by eight. For degree increments, the Cyclone® V device can shift all output frequencies in increments of at least 45°. Smaller degree increments are possible depending on the frequency and divide parameters.