Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

6.3.1. Guideline: Using DQ/DQS Pins

The following list provides guidelines on using the DQ/DQS pins:

  • The devices support DQ and DQS signals with DQ bus modes of x8 or x16. Cyclone® V devices do not support the x4 bus mode.
  • You can use the DQSn pins that are not used for clocking as DQ pins.
  • If you do not use the DQ/DQS pins for memory interfacing, you can use these pins as user I/Os. However, unused HPS DQ/DQS pins on the Cyclone® V SE, SX and ST devices cannot be used as user I/Os.
  • Some specific DQ pins can also be used as RZQ pins. If you need extra RZQ pins, you can use these the DQ pins as RZQ pins instead.
Note: For the x8 or x16 DQ/DQS groups whose members are used as RZQ pins, Altera recommends that you assign the DQ and DQS pins manually. Otherwise, the Intel® Quartus® Prime software might not be able to place the DQ and DQS pins, resulting in a “no-fit” error.

Reading the Pin Table

For the maximum number of DQ pins and the exact number per group for a particular Cyclone® V device, refer to the relevant device pin table.

In the pin tables, the DQS and DQSn pins denote the differential data strobe/clock pin pairs. The DQS and DQSn pins are listed respectively in the Cyclone® V pin tables as DQSX Y and DQSnX Y . X indicates the DQ/DQS grouping number and Y indicates whether the group is located on the top (T), bottom (B), left (L), or right (R) side of the device.

Note: The F484 package of the Cyclone® V E A9, GX C9, and GT D9 devices can only support a 24 bit hard memory controller on the top side using the T_DQ_0 to T_DQ_23 pin assignments. Even though the F484 package pin tables of these devices list T_DQ_32 to T_DQ_39 in the "HMC Pin Assignment" columns, you cannot use these pin assignments for the hard memory controller.