Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

7.1. Enhanced Configuration and Configuration via Protocol

Cyclone® V devices support 1.8 V, 2.5 V, 3.0 V, and 3.3 V programming voltages and several configuration schemes.

Table 92.  Configuration Schemes and Features Supported by Cyclone® V Devices
Mode Data Width Max Clock Rate (MHz) Max Data Rate (Mbps) Decompression Design Security Partial Reconfiguration19 Remote System Update
AS through the EPCS and EPCQ serial configuration device 1 bit, 4 bits 100 Yes Yes Yes
PS through CPLD or external microcontroller 1 bit 125 125 Yes Yes
FPP 8 bits 125 Yes Yes Parallel flash loader
16 bits 125 Yes Yes Yes
CvP (PCIe) x1, x2, and x4 lanes Yes Yes Yes
JTAG 1 bit 33 33

Instead of using an external flash or ROM, you can configure the Cyclone® V devices through PCIe using CvP. The CvP mode offers the fastest configuration rate and flexibility with the easy-to-use PCIe hard IP block interface. The Cyclone® V CvP implementation conforms to the PCIe 100 ms power-up-to-active time requirement.

19 The partial reconfiguration feature is available for Cyclone V E, GX, SE, and SX devices with the "SC" suffix in the part number. For device availability and ordering, contact your local Intel® sales representatives.