Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

5.4.3. LVDS Interface with External PLL Mode

The IP Catalog provides an option for implementing the LVDS interface with the Use External PLL option. With this option enabled you can control the PLL settings, such as dynamically reconfiguring the PLL to support different data rates, dynamic phase shift, and other settings. You must also instantiate the an Altera_PLL IP core to generate the various clock and load enable signals.

If you enable the Use External PLL option with the ALTLVDS transmitter and receiver, the following signals are required from the Altera_PLL IP core:

  • Serial clock input to the SERDES of the ALTLVDS transmitter and receiver
  • Load enable to the SERDES of the ALTLVDS transmitter and receiver
  • Parallel clock used to clock the transmitter FPGA fabric logic and parallel clock used for the receiver rx_syncclock port and receiver FPGA fabric logic
  • Asynchronous PLL reset port of the ALTLVDS receiver