Cyclone® V Device Handbook: Volume 1: Device Interfaces and Integration

ID 683375
Date 10/18/2023
Document Table of Contents

2.5.1. Clocking Modes for Each Memory Mode

Table 10.  Memory Blocks Clocking Modes Supported for Each Memory Mode
Clocking Mode Memory Mode
Single-Port Simple Dual-Port True Dual-Port ROM FIFO
Single clock mode Yes Yes Yes Yes Yes
Read/write clock mode Yes Yes
Input/output clock mode Yes Yes Yes Yes
Independent clock mode Yes Yes
Note: The clock enable signals are not supported for write address, byte enable, and data input registers on MLAB blocks.